Prof. Bae`s R.P.

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  • 15 Y. Hong, M. Wu, J.-H. Bae, S. Hong, Y. Jeong, D. Jang, J. S. Kim, C. S. Hwang, B.-G. Park, and J.-H. Lee "A new sensing mechanism of Si FET-based gas sensor using pre-bias" Sensors and Actuators B: Chemical, vol. 302, p. 127147, doi: 10.1016/j.snb.2019.127147, 2020-01
  • 14 H. Kim, J.-H. Bae, S. Lim, S.-T. Lee, Y.-T. Seo, D. Kwon, B.-G. Park, and J.-H. Lee "Efficient precise weight tuning protocol considering variation of the synaptic devices and target accuracy" Neurocomputing, vol. 378, pp. 189-196, doi: 10.1016/j.neucom.2019.09.099, 2020-02
  • 13 J.-H. Bae, S. Lim, B.-G Park, and J.-H. Lee "High-density and near-linear synaptic device based on a reconfigurable gated Schottky diode" IEEE Electron Device Letters, vol. 38, no. 8, pp. 1153-1156, doi: 10.1109/LED.2017.2713460, 2017-08
  • 12 H.-J. Kang, N. Choi, J.-H. Bae, B.-G. Park, and J.-H. Lee "Analysis of Clockwise and Counter-Clockwise Hysteresis Characteristics in 3-D NAND Flash Memory Cells" IEEE Electron Device Letters, vol. 38, no. 7, pp. 867-870, doi: 10.1109/LED.2017.2705721, 2017-07
  • 11 J. Kim, C.-H. Kim, S. Y. Woo, W.-M. Kang, Y.-T. Seo, S. Lee, S. Oh, J.-H. Bae, B.-G. Park, and J.-H. Lee "Initial synaptic weight distribution for fast learning speed and high recognition rate in STDP-based spiking neural network" Solid-State Electronics, vol. 165, p. 107742, doi: 10.1016/j.sse.2019.107742, 2020-03
  • 10 J.-M. Park†, J.-H. Bae†, J.-H. Eum, S. H. Jin, B.-G. Park, and J.-H. Lee,(†These authors equally contributed to this work) "High-Density Reconfigurable Devices With Programmable Bottom-Gate Array" IEEE Electron Device Letters, vol. 38, no. 5, pp. 564-567, doi: 10.1109/LED.2017.2679343, 2017-03
  • 9 S. Y. Woo, K.-B. Choi, J. Kim, W.-M. Kang, C.-H. Kim, Y.-T. Seo, J.-H. Bae, B.-G. Park, and J.-H. Lee "Implementation of homeostasis functionality in neuron circuit using double-gate device for spiking neural network" Solid-State Electronics, vol. 165, p. 107741, doi: 10.1016/j.sse.2019.107741, 2020-03
  • 8 Y.-T. Seo, M.-K. Park, J.-H. Bae, B.-G. Park, and J.-H. Lee "Implementation of Synaptic Device Using Various High-k Gate Dielectric Stacks" Journal of Naniscience and Nanotechnology, vol. 20, no. 7, pp. 4292-4297, doi: 10.1166/jnn.2020.17788, 2020-07
  • 7 J. H. Bae, and J.-H. Lee "Dual-gate p-GaN gate high electron mobility transistors for steep subthreshold slope" Journal of Nanoscience and Nanotechnology, vol. 16, no. 5, pp. 4919-4923, doi: 10.1166/jnn.2016.12258, 2016-05
  • 6 S.-M. Joe, J.-H. Bae, C. H. Park, and J.-H. Lee "Modeling of ΔIBL due to random telegraph noise with considering bit-line interference in NAND flash memory" Semiconductor Science and Technology, vol. 29, no. 12, p. 125013, doi: 10.1088/0268-1242/29/12/125013, 2014-11
  • 5 S.-T. Lee, S. Lim, N. Choi, J.-H. Bae, D. Kwon, H.-S. Kim, B.-G. Park, and J.-H. Lee "Effect of Word-Line Bias on Linearity of Multi-Level Conductance Steps for Multi-Layer Neural Networks Based on NAND Flash Cells" Journal of Nanoscience and Nanotechnology, vol. 20, no. 7, pp. 4138-4142, doi: 10.1166/jnn.2020.17791, 2020-07
  • 4 G. Kim, E. Park, J. H. Kim, J.-H. Bae, D. H. Kang, and B.-G. Park "Analysis of trap and its impact on InGaN-based blue light-emitting diodes using current-transient methodology" Japanese Journal of Applied Physics, vol. 53, no. 6, p. 062101, doi: 0.7567/JJAP.53.062101, 2014-05
  • 3 K. Lee†, J.-H. Bae†, S. Kim, J.-H. Lee, B.-G. Park, and D. Kwon, (†These authors equally contributed to this work) "Ferroelectric-Gate Field-Effect Transistor Memory with Recessed Channel" IEEE Electron Device Letters, vol. 41, no. 8, pp. 1201-1204, doi: 10.1109/LED.2020.3001129, 2020-08
  • 2 J.-K. Lee, J.-W. Lee, J.-H. Bae, J. Park, S.-W Chung, J. S. Roh, S.-J. Hong, and J.-H. Lee "Phenomenological Analysis of Random Telegraph Noise in Amorphous TiOx-Based Bipolar Resistive Switching Random Access Memory Devices" Journal of Nanoscience and Nanotechnology, vol. 12, no. 7, pp.5392-5396, doi: 10.1166/jnn.2012.6249, 2012-07
  • 1 J.-H. Bae, D. Kwon*, S. Cheema, A. J. Tan, C. Hu, and S. Salahuddin*, (*co-corresponding authors) "Highly Scaled, High Endurance, Ω-Gate, Nanowire Ferroelectric FET Memory Transistors" IEEE Electron Device Letters, vol. 41, no. 11, pp. 1637-1640, doi: 10.1109/LED.2020.3028339, 2020-11